Modelsim/MATLAB Co-simulation of a QoS Multi-core Image Processing System using on-Chip Interconnect

The use of rapid prototyping tools such as MATLAB-Simulink and VHDL-Modelsim becomes progressively more essential for system-on-chip (SoC) design verification because of time-to-market constraints. This paper presents a Modelsim/MATLAB Co-simulation for image processing in multi-core systems (MCSoC) with QoS requirements. The methodology aims to improve the design verification efficiency for image encoder system based on a 2D-Mesh network-onchip (NoC). It presents architecture for image compression and decompression with low complexity for multimedia applications. Our contribution is two folds. First, a low complexity chain is used to reduce the number of DCT coefficients in each block of the image to be computed, quantized and encoded. Second, compression settings can be changed at runtime in order to allow a dynamic adjustment of the trade-off between processing time and image distortion using Modelsim/ MATLAB Co-simulation environment. We discuss in depth the architecture of both proposed image compression scheme and the 2D-Mesh NoC which are planned to reach high performance. The experiments results show that the proposed solution can achieve a reasonable image quality with lower processing time.